1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a fabrication method thereof. More particularly, the exemplary embodiments relate to a three-dimensional non-volatile memory device comprising a plurality of memory cells stacked vertically from a substrate and a fabrication method thereof.
2. Description of the Related Art
Non-volatile memory devices are memory devices that maintain data stored therein even when the power supply is cut off. Currently, various non-volatile memory devices, for example, flash memories, are being widely used.
As an increase in the integration density of two-dimensional memory devices having single-layer memory cells formed on a semiconductor substrate has recently become infeasible, three-dimensional non-volatile memory devices having a plurality of memory cells formed along channel layers protruding vertically from a semiconductor substrate have been proposed.
In conventional three-dimensional non-volatile memory devices, the channel layer is generally formed using non-doped polysilicon, and the source and drain regions are formed by n-type doping. Because these memory devices are not provided with a hole-supply source capable of supplying sufficient holes to the memory cells, the erase operation of the memory cells may not be smooth.
In an attempt to resolve this concern, a method for erasing memory cells using a GIDL (Gate-Induced Drain Leakage) current was proposed. However, even this method may not supply sufficient holes to the memory cells during the erase operation of the memory cells. In addition, the use of the GIDL current has a concern regarding the deterioration of properties of the device due to program/erase cycling.